Full-chip electrical parasitic extraction of on-chip metal wires using an electronic design automation (EDA) tool is an important step in the design of an integrated circuit (IC). Depending on the designer's preference for accuracy or efficiency, either an implementation-level or a signoff-level parasitic extraction is performed. Implementation-level extractors may be typically 2 to 5 times faster than signoff-level extractors, but their accuracy may be, for example, 2 to 3 times worse.
In addition to decreased overall accuracy, implementation-level extractors typically lack proper support for a number of advanced process effects or layout attributes. One such attribute may be a floating metallization added to ensure uniformity of layout density and adequate layer planarization. Implementation-level extractors may approximate floating metallization as grounded conductors, thus further compromising their accuracy. Signoff-level parasitic extractors may provide an accuracy to within a few percent of silicon measurements or reference field solver data. In order for an EDA tool to satisfy signoff requirements, ideally it should provide a high degree of accuracy over many technology nodes and possible layout styles. This poses a challenging task since for every new process technology, new process effects need to be supported by signoff-level extractors.
Parasitic extraction software are further classified as providing either a full or incremental extraction. A full extraction process involves characterization of all objects or nets disposed in the IC. Conversely, incremental extraction only characterizes nets that have changed since the last iteration in the design process. An incremental extraction may be typically 2 to 10 times faster than a full extraction for a layout change of, for example, 1 to 5%. The efficiency of incremental extractors is important since they are typically bundled as part of a place and route and other tools operating in an incremental and faster mode. Conventional incremental extractors provide minimum runtime benefit and have a significantly degraded accuracy when used during a signoff process. The output of a parasitic extraction tool is often used by a downstream tool to estimate, for example, the performance, power consumption, and reliability of the IC design.
The following is a definition of a number of terms used in the present application:
Place & route (P&R) system:Software that facilitates the automated placement androuting of an integrated circuit (IC)Layout:Topology of metal interconnectionsParasitic Extraction:Calculation of interconnect parasitic effects in the form ofresistance, inductance, and capacitanceImplementation Mode;Faster, less accurate mode used for analysis in early stagesof P&R design processSignoff Mode:Relatively slower, more accurate mode used for analysis inlater stages of P&R design processECOEngineering change order (ECO) describing a singlephysical change to a designVictim NetA single metal interconnection providing connectivitybetween a set of inputs and outputsAggressor NetAny net whose existence influences the parasitics of one ormore victim netsECO NetAny net whose topology has changed in successive designiterationsECO Affected NetAny net whose parasitics are changed due to its proximityto one or more ECO netsPlaceholder NetAny net whose topology is not changed and has minimal orno coupling to an ECO netFull extractionParasitic extraction of all nets contained within an ICIncremental extractionParasitic extraction of only ECO and ECO affected nets
Conventional techniques for providing incremental extraction solution involve expanding the area in which the change has occurred by a predefined distance to form a region that surrounds the change, referred to herein as the halo region. FIG. 1A is a partial view of a number of metal interconnects disposed in the same layer in layout 10 of an IC. FIG. 1B is the partial view of the same metal interconnects in layer after the inclusion of a buffer in region 15 to resolve a violation identified during static timing analysis. The rectangles or polygons corresponding to non-ECO nets disposed in region 15 define the extent of ECO affected nets. As is seen by comparing FIGS. 1A and 1B, to accommodate the inclusion of the buffer, changes are made in metal interconnects 12 and 14. Consequently, although the changes are localized, a relatively small change in one polygon can result in the addition of many ECO affected nets.
An IC is often fabricated using a multi-layer (e.g., 10 layers) process. To maintain signoff-level accuracy, the effect that the changes in one layer may cause on other layers need to be considered. FIG. 2A is a partial view of a number of metal interconnects disposed in a layer 40 of an IC. Assume that a number of interconnect changes are made in region 50 of FIG. 2A. FIG. 2B is the partial layout view of another metal layer 50 of the IC shown in FIG. 2A. Changes made to the metal interconnects in region 50 of layer 40 of FIG. 2A are shown as causing changes in region 55 of layer 60 of FIG. 2B. Accordingly, FIGS. 2A and 2B show the impact the metal interconnect change in one layer can cause in the metal interconnects of another layer. As each layer-to-layer interaction is accounted for, the number of aggressor nets impacted can grow dramatically even from a relatively small topological change.
To limit the number of aggressor nets, simplifications need to be made. Such simplification include, for example, reducing the size of the halo region, or restricting/eliminating cross layer checking. Such simplifications while reducing the runtime, severely impact the accuracy and the signoff quality of the extraction.
FIG. 3A is a partial layout view of a number of metal interconnects 90 (also referred to herein as nets or metal traces) disposed in a layer of an IC. Net 70 is shown as an ECO net and nets 82, 84, 86 and 88 are identified as aggressor nets. FIG. 3B is a partial layout view of metal interconnects 90 after an increase in the length of ECO net 70 on the same layer.
Due to their proximity, aggressor nets (shown in the Figure as Aggr) 88 and 86 are directly impacted by the change in ECO net 70's length increase and thus experience an increase in their couplings to the ECO net 70. Aggressor net 84 is not directly impacted by the change in length of the ECO net 70, but it is indirectly affected due the second neighbor coupling effect. In other words, aggressor net 84 is affected by aggressor net 86 as a result of the increased coupling between ECO net 70 and aggressor net 86. Second neighbor coupling is smaller than direct coupling so the net change in coupling between ECO net 70 and aggressor net 84 may be negligible. The change in coupling between aggressor net 82 and ECO net 70 is a combination of second and third neighbor coupling and is negligible.
Of the four aggressor nets shown in FIGS. 3A and 3B, aggressor nets 88 and 86 are in the direct line-of-sight of ECO net 70 and thus are impacted the most by the change in the length of ECO net 70. Conventional EDA tools only consider nets that are in the direct line-of-sight of a changed ECO net and thus are unable to account for a relatively high degree of second or higher order intra-layer (i.e., same layer) or inter-layer (i.e., different layer) coupling between the nets.